In the CDMA method, communications can be performed based on a system that all users simultaneously share the same frequency band using different spread codes assigned to the users. However, due to a cross correlation between spread codes assigned to different users, the signal of one user works as an interference signal to another users. The degree of cross interference becomes higher in association with an increase in the number of users. This degrades the reception characteristic. As a method for overcoming this problem, a multistage serial interference canceller system (henceforth, a serial interference canceller system) is conventionally known.
In the serial interference canceller system the reception characteristic is improved by enhancing the signal-power to interference-power ratio (SIR) for users for the following processing. Precisely, in this method, transmission data is temporarily determined in decreasing order of its received power, a replica of the interference signal is generated in the reception side based on the temporarily determined data. Finally, the interference-signal replica is subtracted from the incoming signal.
In this method, it is required that the above mentioned operation is repeated by times corresponding to the number of users in order to reduce the influence exerted on interference cancellation by an error in temporary determination and a remaining interference component. Accordingly, this method is referred to as a serial interference canceller. This serial interference canceller is required to perform channel estimation with high accuracy in order to reproduce the replica of the interference signal. Accordingly, a frame structure obtained by inserting a pilot symbol in the information is employed. The operation of estimating a channel using this frame structure is also repeated by times corresponding to the number of users. Thus, the degree of accuracy of channel estimation is improved by successively performing channel estimation in each stage.
FIG. 16 and FIG. 17 show a CDMA reception system applying a conventional serial canceller, that is, an interference cancellation device disclosed in Technical Report of IEICE RCS95-50, the institute of electronics, information and communication engineers as an example. This conventional CDMA reception system comprises, a sorting circuit 3; an interference cancellation device having K (natural number) number of blocks of a first stage to a final stage 4, 5 to 6, (K−1) units of delay circuits 7, 8 . . . , K units of matched filters (MF) 20A1 to 20AK, and K units of level detectors 21A1 to 21AK; a decoder 9; SIR measurement block 10; and TPC bit generator 11.
The sorting circuit 3 determines the ranking of the users (#1 to #K) in descending order of the incoming signal level and thus sorts the users. The first to the final stages 4, 5 to 6, which are serially connected to generate replicas of interference signals based on the incoming signals, sequentially execute interference cancellation according to the ranking of the users. The delay circuits 7, 8 . . . delay the incoming signals by a time equivalent to the processing time for generating replicas of interference signals required up to the previous stage when the incoming signals are to be output to the second stage 5 and the stages from then on. The decoder 9 de-interleaves and Viterbi-decodes based on data judged values DJ1 to DJK output from the final stage 6.
The SIR measurement block 10 measures the SIR based on respective data judged values DJ1 to DJK output from the final stage 6. The TPC bit generator 11 determines a TPC bit value based on the result of respective judgements in the SIR measurement block 10 and a previously provided target SIR. The TPC bit mentioned here indicates data transmitted to a mobile station on downlink transmission signals. The matched filters 20A1 to 20AK detect correlation values for users from the incoming signals. The level detectors 21A1 to 21AK detect the levels of the incoming signals based on the correlation values for each user detected in the matched filters 20A1 to 20AK, and outputs the detected levels to the sorting circuit 3 in the following stage.
The first stage 4 comprises delay circuits 4A2, 4A3 to 4AK, subtracters 4B2, 4B3 to 4BK, and first to K-th processing units 4C1, 4C2 to 4CK. Each of the delay circuits 4A2, 4A3 to 4AK receives the incoming signal as an error signal as it is, and delays this signal for a time equivalent to the processing time required for generating all the replicas of the interference signals for users whose processing sequence is preceded in the same stage. Each of the subtracters 4B2, 4B3 to 4BK subtracts all the replicas of interference signals for the users whose processing sequence is preceded, except a relevant user, from the output (delayed incoming signal) of the delay circuit in the previous stage for output.
Each of the first to K-th processing units 4C1, 4C2 to 4CK restores the replica of the interference signal by performing inverse spread, channel estimation by a pilot symbol, RAKE synthesis, and identification based on received user signals ranked in descending order of the level of the incoming signal. Output (replica of the interference signal) of each of the first to K-th processing units 4C1, 4C2 to 4CK is supplied to all the subtracters that require the replica of the interference signal, of the subtracters associated with users whose processing sequence is delayed, not only in the same stage but also the following stages.
FIG. 18 shows a frame structure of the incoming signal obtained by inserting a pilot symbol in the information. One frame of the incoming signal consists of a pilot symbol, a TPC symbol, and a data symbol. One pilot block is structured by adding the pilot symbol at the head position of the following block to the frame. The range of the block includes variations frontward or backward due to phase shift as shown in FIG. 18.
Operation of the CDMA reception system is explained below. FIG. 16 and FIG. 17 show the case in which the number of users is K (natural number). The incoming signal is input into each of the matched filters 20A1 to 20AK corresponding to each user. The matched filters 20A1 to 20AK obtain correlation values by users, and the level detectors 21A1 to 21AK in the following stage measure the respective levels of the incoming signals for each user. These level detectors 21A1 to 21AK output the results of measured received signal level for each user to the sorting circuit 3. The sorting circuit 3 sorts the incoming signals in descending order based on the level the of incoming signals, and temporarily determines transmission data in that order.
An interference cancellation section formed by the plurality of stages (first stage 4 to final stage 6) is serially connected to the sorting circuit 3 in its downstream side, and interference cancellation is sequentially executed in each of the stages. Interference cancellation is started in the first stage 4. In this first stage 4, the first processing unit 4C1 is allocated to the processing for a user signal (the incoming signal) with the highest signal level. When this user signal is input into the first processing unit 4C1, inverse spread, channel estimation by its pilot symbol, RAKE synthesis, and identification and judgement are performed in the unit.
The judgement value obtained in this manner is spread again in each path using an estimated value of variation in a transmission path, and the replica of an interference signal for any user signal whose incoming signal level is the highest is generated. This interference-signal replica is supplied, as output of the first processing unit 4C1, to all of the other processing units 4C2 to 4CK that are to perform the following processing in the same stage. In this manner, the replica of the interference signal, that is output from the first processing unit 4C1, is used for generating the replica of an interference signal for any user signal whose incoming signal level is lower than this user signal. During generation of replicas, this replica is also used for generating the replica of the interference signal from the incoming signal for some other user.
A relation between the pilot symbol used for channel estimation and the data symbol is explained below. In each of the stages 4, 5 to 6, interference cancellation and generation of the replica of the interference signal are performed in each pilot block (see FIG. 18). A reception-fading complex envelope in each location of data symbols can be obtained by interpolating estimated reception-fading complex envelopes in pilot symbols for the data symbol between the pilot symbols, and extrapolating an estimated reception-fading complex envelope in a pilot symbol for the data symbol outside the pilot symbol. The second processing unit 4C2 in the first stage 4 is allocated to any user whose incoming signal level is the second highest in the same manner as explained above.
The incoming signal is delayed in the delay circuit 4A2 for a time equivalent to the processing time in the first processing unit 4C1. The subtracted 4B2 subtracts the replica of the interference signal for the first user obtained in the first processing unit 4C1 is then subtracted from the incoming delayed in signal. The output of the subtracter 4B2 is input into the second processing unit 4C2. The second processing unit 4C2 performs the same processing as that of the first processing unit 4C1 and outputs the replica of the interference signal for the second user.
The third processing unit 4C3 in the first stage is allocated to any user whose incoming signal level is the third highest. In the case of this third user, the incoming signal is delayed in the delay circuit 4A3 for a time equivalent to that required for the processing in the first and second processing units 4C1 and 4C2. The replica of the interference signal for the first user and the replica of the interference signal for the second user are subtracted from the delayed incoming signal in the subtracter 4B3. The result of the computation is input into the third processing unit 4C3. The same processing as that in the first and second processing units 4C1 and 4C2 is performed in the third processing unit 4C3 and the replica of the interference signal for the third user is then output. By repeating such operation up to the K-th user, the processing for generating replicas of the interference signals in the processing units 4C1 to 4CK corresponding to all the users is completed in the first stage.
In the second stage 5, the processing for generating replicas of interference signals of the incoming signals for all users is performed again. The incoming signal is supplied to the second stage 5 after delaying in the delay circuit 7 for a time equivalent to that required for the processing in the first stage 4. The replicas of the interference signals for the second user, the third user to the K-th user in the first stage 4 are subtracted from the received signal (received pilot block) in a subtracter 5B1 provided downstream from the delay circuit 7. The result of the computation is input into a first processing unit 5C1. The same processing as that in each processing unit of the first stage 4 is performed in the first processing unit 5C1 and the interference-signal replica for the first user in the second stage 5 is then output.
The incoming signal delayed in the delay circuit 7 is further delayed in a delay circuit 5A2 for a time equivalent to that required for the processing in the first processing unit 5C1 and is input into a subtracter 5B2 in the second stage 5. The replicas of the interference signals for the third user to the K-th user in the first stage 4 and the replica of the interference signal for the first user in the second stage 5 are then subtracted from the delayed incoming signal. The result of the computation is input into a second processing unit 5C2, and an interference-signal replica for the second user in the second stage 5 is generated.
A third processing unit 5C3 in the second stage 5 is allocated to a third user. In the case of this third user, the incoming signal is delayed in a delay circuit 5A3 for a time equivalent to that required for the processing in the first and second processing units 5C1 and 5C2. The interference-signal replica for the first user and the interference-signal replica for the second user are subtracted from the delayed incoming signal in a subtracter 5B3. The result of the computation is input into the third processing unit 5C3. The same processing as that in the first and second processing unit 5C1 and 5C2 is performed in the third processing unit 5C3, and the interference-signal replica for the third user is output. By repeating the same operation up to the K-th user, the processing for generating replicas of interference signals in the first to K-th processing units 5C1 to 5CK corresponding to all the users is completed in the second stage 5.
The same processing as in the second stage is performed in each stage after the second stage and on except the final stage. Therefore, the processing in the final stage will only be explained here with reference to FIG. 17. The processing for generating replicas of interference signals with respect to incoming signals for all the users are performed again in the final stage 6. The incoming signal is delayed for a time equivalent to that required for all the processing in the first to K-th stages in the delay circuits 7, 8 . . . (K−1), and is supplied to the final stage 6. The replicas of interference signals for all the users except the first user are subtracted from the incoming signal (received pilot block) delayed in the previous stage in a subtracter 6B1 of the final stage 6. The result of the computation is input into a first processing unit 6C1. The same processing as that in each of the processing units is performed in the first processing unit 6C1 and then the interference-signal replica for the first user is output in the final stage 6.
The delayed incoming signal in the previous stage is further delayed in a delay circuit 6A2 for a time equivalent to that required for the processing in the first processing unit 6C1 and input into a subtracter 6B2 of the final stage 6. The replicas of the interference signals for all the users except the second user are then subtracted from the delayed incoming signal. The result of the computation is input into a second processing unit 6C2, and an interference-signal replica for the second user in the final stage 6 is generated.
A third processing unit 6C3 in the final stage 6 is allocated to a third user. In the case of this third user, the incoming signal is delayed in a delay circuit 6A3 for a time equivalent to that required for the processing in the first and second processing units 6C1 and 6C2. The replicas of the interference signals for all the users except the third user are subtracted from the delayed incoming signal in a subtracter 6B3. The result of the computation is input into the third processing unit 6C3. The same processing as that in the first and the second processing units 6C1 and 6C2 is performed in the third processing unit 6C3, and the interference-signal replica for the third user is output. By repeating the same operation up to the K-th user, the processing for generating replicas of interference signals in the first to K-th processing units 6C1 to 6CK corresponding to all the users is completed in the final stage 6.
Thus, the reception characteristic is improved in each stage by subtracting the replicas of the interference signals for the other users, that have been generated in the previous stages, from the incoming signal. According, the degree of accuracy of channel estimation becomes higher as the processing approaches the final stage. Therefore, output with the highest degree of accuracy in channel estimation, that is, the judgement values DJ1 to DJK after interference cancellation is processed, are obtained in the final stage 6. The decoder 9 and the SIR measurement block 10 are connected to the final stage 6. The data is subjected to the processing for de-interleave and Viterbi decoding in the decoder 9 based on the judgement values DJ1 to DJK for respective users output from the final stage 6 to obtain decoded data.
These judgement values DJ1 to DJK are also supplied to the SIR measurement block 10, and SIR of the incoming signal for every user is measured based on the judgement values DJ1 to DJK for that particular user. The SIR for each user measured in the SIR measurement block 10 is output to the TPC bit generator 11, and the SIR measured in the SIR measuring device 10 is compared with the previously provided target SIR. As a result, TPC bit, that instructs to step down transmission power in a mobile station, is generated for any user with the measured SIR higher than the target SIR, whereas TPC bit, that instructs to step up transmission power in a mobile station, is generated for any user with the measured SIR lower than the target SIR. The TPC bit for every user produced in this manner is transmitted to the relevant mobile station on the downlink transmission signal. The processing is executed in each pilot block.
Since the conventional interference cancellation device is configured as explained above, the effect of interference cancellation by the serial interference canceller is dependent on for which user the processing for inverse spread, channel estimation, and generation of an interference-signal replica is first performed in the stages 4, 5, . . . 6 shown in FIG. 16 and FIG. 17. Therefore, conventionally, in order to obtain the sequence, incoming signal power for all users is measured prior to the processing in each stage, a user with the highest power is ranked first, and the sequence is determined according to the measured signal power.
On the other hand, SIR used for controlling transmission power is measured based on the result of determination of a incoming signal for each user after all the processing for interference cancellation is finished. Thus, the device for measurement of the signal power is utilized just for determining the sequence. However, if this device is used only for determining the sequence, then there arises a problems that a lot of time is required for the measurement of power and the ranking process. As a consequence a delay is generated in data demodulation, the scale of hardware becomes larger so that power consumption becomes larger, and so forth. Further, as shown in FIG. 16 and FIG. 17, the power measurement block is formed with the matched filters 20A1 to 20AK and the level detectors 21A1 to 21AK. Therefore, there has been a concern that cross interference between users may cause a greater measurement error in measurement of incoming signal power.